1. Field of the Invention
The present invention relates to a semiconductor memory device and, particularly, to a dynamic type semiconductor memory device that requires a refresh operation for data retention. More specifically, the present invention relates to a configuration for reducing current consumption during a stand-by state, particularly, in a data holding mode.
2. Description of the Background Art
In a dynamic semiconductor memory device (DRAM: Dynamic Random Access Memory), data is stored in a capacitor in the form of charges. At accessing of data in a memory cell, the charges stored in the capacitor are read to a corresponding bit line. The bit line is precharged at a predetermined voltage level in a standby state. A sense amplifier provided in correspondence to the bit line detects the voltage change generated on the bit line and the memory cell data is read. The voltage of the bit line fully swings by the amplification operation of the sense amplifier, so that data is rewritten to the memory cell.
In DRAM, a shared sense amplifier configuration is generally employed, in which a memory cell array is divided into blocks and adjacent blocks share sense amplifiers so as to decrease the load of sense amplifiers. A selected memory block including a selected memory cell is connected to the corresponding sense amplifiers, and the unselected memory block which shares the sense amplifiers with the selected memory block is isolated from the corresponding sense amplifiers. In order to perform this connection/isolation between the sense amplifier and the bit line of the memory block, a bit line isolation gate is provided for each bit line.
In order to drive the bit line to power supply voltage level by the sense amplifier, a signal having a high voltage level higher than a sense power supply voltage is applied, as a bit line isolation control signal, to this bit line isolation gate. A configuration intended to reduce current consumption in generating a bit line isolation control signal at a high voltage level is disclosed in, for example, Prior Art Document 1 (Japanese Patent Laying-Open No. 6-28856). According to Prior Art Document 1, the bit line isolation control signal is maintained at power supply voltage level in a standby state and driven to a high voltage level when a selected memory cell is connected to a sense amplifier. In a refresh mode for holding data, the voltage of the bit line isolation control signal for a selected memory block is boosted from the power supply voltage level to high voltage level at starting of a sensing operation, the boosting is stopped after the completion of the sensing operation, and the bit line isolation control signal is maintained at the power supply voltage level. Thus, a time period in which the bit line isolation control signal at the high voltage level is generated is shortened, thereby reducing current consumption.
Further, Prior Art Document 2 (Japanese Patent Laying-Open No. 9-63266) discloses a configuration intended to reduce current consumption in a self refresh mode for periodically performing a refresh operation internally. According to Prior Art Document 2, after memory cell data is transmitted to a sense amplifier in the self refresh mode, a bit line is isolated from the sense amplifier. In this state, the sense amplifier is activated. The sense node of the sense amplifier is isolated from the bit line, and, therefore, the parasitic capacitance at the sense node is small, a sensing operation is performed at high speed, a through current flowing from the sense power supply node of the sense amplifier to the sense ground node thereof during a transition state is decreased, and current consumption is thereby reduced. After the completion of the sensing operation, a bit line isolation instruction signal is driven to the high voltage level, and data latched by the sense amplifier is written to an original memory cell.
According to Prior Art Documents 1 and 2 described above, the manner of generating the bit line isolation control signal at the refresh mode is different from that in a normal operation mode. According to Prior Art Document 1, the consumption of current required to boost the voltage of the bit line isolation control signal is intended to be reduced. According to Prior Art Document 2, the through current of the sense amplifier is intended to be reduced in the sensing operation. However, these Prior Art Documents 1 and 2 fail to consider the current consumption due to the existence of a leakage path caused by a particle (contaminant) such as etching residue in a manufacturing process.
In the DRAM, word lines and bit lines are arranged in directions crossing each other. When a particle remains in a manufacturing process, a word line may be electrically connected to a corresponding bit line through the contaminant. When this contaminant is an electric conductor, the word line is short-circuited to the bit lines. When this short circuit is low-resistive, the selected word line is not driven to a select state in the DRAM or the voltage level of the bit line is fixed by the unselected word line, thus causing malfunctions such as a state where memory cell data cannot be read. As a result, the DRAM is identified as a defective product during a test.
When this short circuit is a high resistance, the DRAM operates normally. However, even when this short circuit is the high resistance, the word line is electrically connected to the bit line, and therefore, in a standby state, when the bit lines are precharged at a predetermined voltage level, a current flows from the bit line to the word line through the high resistance of the short circuit.
In a standby state, the sense amplifier is electrically disconnected from sense power source lines (a sense power supply line and a sense ground line). However, the common source node of the sense amplifier (connection node connected to a sense amplifier activation transistor) is precharged at the same voltage level as that of the bit line. In the standby state, the bit line isolation gate is made conductive, so that a current flows from the common source node of the sense amplifier to the word line through the bit line and the high resistance.
When the DRAM is applied to portable equipment driven by a battery, DRAM is required to have a very low standby current or ultra low standby current according to the specification of the applied system. In this case, the quantity of a leakage current through the high resistance becomes significantly innegligible. In an operation mode such as a self refresh mode for holding data, in particular, data is not accessed but only held. Therefore, it is required to further reduce current consumption in view of the life of the battery.
Although Prior Art Documents 1 and 2 described previously intend to reduce current consumption in the refresh mode, they do not consider the problem of the leakage current flowing between a word line and a bit line through the high resistance.